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Silicon Labs /SiM3_NRND /SIM3U167_B /FLASHCTRL_0 /TCONTROL

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Interpret as TCONTROL

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https://regviz.com/r/Silicon Labs/SiM3_NRND/SIM3L168_A/FLASHCTRL_0/TCONTROL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLOW)FLRTMD

FLRTMD=SLOW

Description

Flash Timing Control

Fields

FLRTMD

Flash Read Timing Mode.

0 (SLOW): Configure the Flash read controller for AHB clocks below 20 MHz.

1 (FAST): Configure the Flash read controller for AHB clocks above 20 MHz.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data